How Many General Purpose Registers Does The Arm Processor Have
The amount of registers depends on the ARM version. According to the ARM Reference Manual, there are 30 general-purpose 32-bit registers, with the exception of ARMv6-1000 and ARMv7-Yard based processors. The first 16 registers are attainable in user-level style, the additional registers are bachelor in privileged software execution (with the exception of ARMv6-M and ARMv7-G). In this tutorial serial nosotros will work with the registers that are accessible in any privilege mode: r0-fifteen. These 16 registers can exist divide into two groups: general purpose and special purpose registers.
The following tabular array is just a quick glimpse into how the ARM registers could relate to those in Intel processors.
R0-R12: can exist used during common operations to store temporary values, pointers (locations to retentiveness), etc. R0, for example, can be referred as accumulator during the arithmetic operations or for storing the result of a previously chosen function. R7 becomes useful while working with syscalls as information technology stores the syscall number and R11 helps us to go along rails of boundaries on the stack serving as the frame pointer (will be covered after). Moreover, the part calling convention on ARM specifies that the get-go four arguments of a function are stored in the registers r0-r3.
R13: SP (Stack Arrow). The Stack Pointer points to the top of the stack. The stack is an expanse of memory used for function-specific storage, which is reclaimed when the role returns. The stack arrow is therefore used for allocating space on the stack, by subtracting the value (in bytes) we want to allocate from the stack pointer. In other words, if we want to classify a 32 bit value, we subtract 4 from the stack pointer.
R14: LR (Link Annals). When a function phone call is made, the Link Register gets updated with a memory address referencing the adjacent education where the function was initiated from. Doing this allows the programme return to the "parent" function that initiated the "child" part telephone call after the "child" function is finished.
R15: PC (Program Counter). The Program Counter is automatically incremented by the size of the instruction executed. This size is always 4 bytes in ARM state and two bytes in Thumb mode. When a branch instruction is beingness executed, the PC holds the destination address. During execution, PC stores the accost of the current instruction plus eight (two ARM instructions) in ARM state, and the current pedagogy plus 4 (ii Thumb instructions) in Thumb(v1) state. This is unlike from x86 where PC always points to the next instruction to be executed.
Let's expect at how PC behaves in a debugger. Nosotros use the following program to shop the accost of pc into r0 and include two random instructions. Permit'south see what happens.
.section .text .global _start _start: mov r0, pc mov r1, #2 add r2, r1, r1 bkpt
In GDB we set a breakpoint at _start and run information technology:
gef> br _start Breakpoint ane at 0x8054 gef> run
Here is a screenshot of the output we meet first:
$r0 0x00000000 $r1 0x00000000 $r2 0x00000000 $r3 0x00000000 $r4 0x00000000 $r5 0x00000000 $r6 0x00000000 $r7 0x00000000 $r8 0x00000000 $r9 0x00000000 $r10 0x00000000 $r11 0x00000000 $r12 0x00000000 $sp 0xbefff7e0 $lr 0x00000000 $pc 0x00008054 $cpsr 0x00000010 0x8054 <_start> mov r0, pc <- $pc 0x8058 <_start+iv> mov r0, #2 0x805c <_start+8> add r1, r0, r0 0x8060 <_start+12> bkpt 0x0000 0x8064 andeq r1, r0, r1, asr #10 0x8068 cmnvs r5, r0, lsl #2 0x806c tsteq r0, r2, ror #18 0x8070 andeq r0, r0, r11 0x8074 tsteq r8, r6, lsl #6
Nosotros can see that PC holds the address (0x8054) of the adjacent didactics (mov r0, pc) that volition be executed. At present let'southward execute the next instruction afterwards which R0 should hold the accost of PC (0x8054), right?
$r0 0x0000805c $r1 0x00000000 $r2 0x00000000 $r3 0x00000000 $r4 0x00000000 $r5 0x00000000 $r6 0x00000000 $r7 0x00000000 $r8 0x00000000 $r9 0x00000000 $r10 0x00000000 $r11 0x00000000 $r12 0x00000000 $sp 0xbefff7e0 $lr 0x00000000 $pc 0x00008058 $cpsr 0x00000010 0x8058 <_start+iv> mov r0, #2 <- $pc 0x805c <_start+8> add r1, r0, r0 0x8060 <_start+12> bkpt 0x0000 0x8064 andeq r1, r0, r1, asr #ten 0x8068 cmnvs r5, r0, lsl #two 0x806c tsteq r0, r2, ror #18 0x8070 andeq r0, r0, r11 0x8074 tsteq r8, r6, lsl #6 0x8078 adfcssp f0, f0, #four.0
…right? Incorrect. Look at the address in R0. While we expected R0 to contain the previously read PC value (0x8054) it instead holds the value which is two instructions ahead of the PC we previously read (0x805c). From this example you can run into that when we straight read PC it follows the definition that PC points to the adjacent pedagogy; simply when debugging, PC points two instructions ahead of the current PC value (0x8054 + viii = 0x805C). This is considering older ARM processors always fetched 2 instructions ahead of the currently executed instructions. The reason ARM retains this definition is to ensure compatibility with earlier processors.
Source: https://azeria-labs.com/arm-data-types-and-registers-part-2/
Posted by: lopezdecul1995.blogspot.com
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